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dc.contributor.advisorAtoofian, Ehsan
dc.contributor.authorJeyakumaran, Thireshan
dc.date.accessioned2016-01-07T17:51:53Z
dc.date.available2016-01-07T17:51:53Z
dc.date.created2015
dc.date.issued2016-01-07
dc.identifier.urihttp://knowledgecommons.lakeheadu.ca/handle/2453/708
dc.description.abstractWith the rise of chip multiprocessors (CMPs), it is necessary to use parallel programming to exploit computational power of CMPs. Traditionally, lock-based mechanisms have been used to synchronize shared variables in parallel programs. However, with the complexity associated with locks, writing a correct parallel program is a huge burden for programmers. As an alternative, Transactional Memory (TM) is gaining momentum as a parallel programming model for multi--‐core processors. TM provides programmers with an atomic construct (transaction), which can be used to guarantee atomicity of accesses to shared variables, as the synchronization is handled through the underlying system. Transactional memory comes in two variants: Software transaction memory (STM) and Hardware transaction memory (HTM). Both STM and HTM systems have advantages and disadvantages that either enhance or penalize performance in transactional applications. In this thesis, the focus is on implementing an adaptive system that exploits both STM and HTM at transaction granularity. The goal is to achieve performance gain by incorporating the benefits of both TM systems. A synchronization technique is developed to seamlessly switch between HTM and STM based on the characteristics of a transaction. We exploit decision tree to predict the optimum system for each transaction in a given application. The decision tree is a form of supervised machine learning to classify transactions based on parameters such as transaction size, transaction write ratio, etc. From the evaluations using STAMP, NAS, and DiscoPoP benchmark suites, the proposed adaptive system is able to improve speed of transactional applications by 20.82% on average.en_US
dc.language.isoen_USen_US
dc.subjectTransactional memory (TM)en_US
dc.subjectchip multiprocessors (CMP)en_US
dc.subjectsynchronizationen_US
dc.titleImproving Performance of Transactional Applications through Adaptive Transactional Memoryen_US
dc.typeThesis
etd.degree.nameMasters of Science in Electrical and Computer Engineeringen_US
etd.degree.levelMasteren_US
etd.degree.disciplineEngineeringen_US
etd.degree.grantorLakehead Universityen_US


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