The design of a multi-loop, low-power low dropout voltage regulator with zero-pole tracking technique - Williams, Zakary (My University, 2024)
This thesis describes the theoretical background, design, simulation, implementation and measurements of an analog low-dropout voltage regulator intended for wide load applications requiring low power consumption. Due to the modern requirements for systems on chip to be operable over long periods and over wide conditions, circuits have become more efficient to meet such demands. Typically as a regulator design is optimized for low power consumption, the performance is worsened. This tradeoff produces the need for a lowdropout regulator which is capable of wide, stable operation while consuming little current. This work contributes to the state of the art of low power low-dropout regulators, further contributing to the literature by testing and measuring the fabricated design. Finally deepening this research with a comparison of the past decades of research in low-dropout technologies. The proposed work in this thesis is comprised of a low-dropout regulator which utilizes a multi-loop compensation network to increase this stability while consuming very little current. The design introduces Ahuja compensation, which removes the feed-forward path which is common in Miller compensation. Furthermore, a zero-tracking network is proposed, which extends stability by inserting a zero capable of tracking the frequency of the dominant output pole. This multi-loop technique provides a phase margin of 60◦ at the lowest, demonstrating stable operation through the full current range of 0 mA to 50 mA. A schematic and layout is produced with the design being implemented in the TSMC 180 nm standard CMOS process. The measured quiescent current is 486.67 nA with the ability to reduce this further by disabling the circuit operation, allowing for a static current draw of 2.06nA. At its peak, the circuit performs with a current efficiency of 99.96%. With a stepped load transient performance of 418 µs with an overshoot of 52.5 mV between full and no load. With the positive step response being 36.5 µs with a change in output of 81.25mV. [...]