Browsing by Advisor
Now showing items 1-7 of 7
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Boosting performance of transactional memory through transactional read tracking and set associative locks
(2013)Multi-core processors have become so prevalent in server, desktop, and even embedded systems that they are considered the norm for modem computing systems. The trend is likely toward many-core processors with many more ... -
Improving Performance of Transactional Applications through Adaptive Transactional Memory
(2015)With the rise of chip multiprocessors (CMPs), it is necessary to use parallel programming to exploit computational power of CMPs. Traditionally, lock-based mechanisms have been used to synchronize shared variables in ... -
Improving power of L1 data cache and register file utilizing critical path instructions
(2014)As transistor’s feature size shrinks, power becomes one of the limiting factors in design of modern processors. Cache and register file are the two power hungry components in processors, consuming more than one third of ... -
Mitigating the impact of decompression latency in L1 compressed data caches via prefetching
(2017)Expanding cache size is a common approach for reducing cache miss rates and increasing performance in processors. This approach, however, comes at a cost of increased static and dynamic power consumption by the cache. ... -
Nonlinear transient analysis based on power waves and state variables
(2010)Muhammad Ershadul Kabir was born in Chittagong, Bangladesh on July 15, 1982. He received the Bachelor of Science in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) ... -
Optimization of Software Transactional Memory through Linear Regression and Decision Tree
(2015)Software Transactional Memory (STM) is a promising paradigm that facilitates programming for shared memory multiprocessors. In STM programs, synchronization of accesses to the shared memory locations is fully handled by ... -
Power-aware caches for GPGPUs
(2015)In this thesis, we propose two optimization techniques to reduce power consumption in L1 caches (data, texture and constant), shared memory and L2 cache. The first optimization technique targets static power. Evaluation ...
