DVS-capable ultra-low-power subthreshold CMOS temperature sensor / by Gregory Toombs.

Abstract

There are many contemporary contexts in which a small, low-power-consumption temperature sensor is very valuable. Power, area, speed and temperature range factors are important constraints in modern VLSI design. As transistor dimensions decrease, it is possible to lower the operating voltage of circuits, and dynamic voltage scaling (DVS) has been successfully implemented in several commercial applications to reduce power consumption. Power density is increasing, and the resultant temperature issues are being addressed by DVS, considered an efficient dynamic thermal management (DTM) technique. DVS/DTM automation techniques require thermal sensors that operate over a range of supply voltages. Therefore, temperature sensor designs such as this one are needed to address these engineering challenges. In this thesis, a DVS-capable ultra-low-power sub threshold temperature sensor in 180 nm CMOS technology is proposed. The design is composed of a proportional-to-absolute-temperature (PTAT) current generator modified for insensitivity to power supply variation. The design is monolithic; the included reference current generator is a peaking source whose input is fed back from the output of the sensor. The design procedure includes empirical parameter extraction from BSIM simulations to yield a transistor model viable for design calculations, and adjustments to biasing and transistor dimensions to minimize power consumption and maintain adequate voltage supply independence and linearity. The design utilizes the exponential characteristics of sub threshold CMOS transistors to construct an output current that is a firstorder Taylor approximation proportional to the thermal voltage. This is the first time such a design scheme is presented.