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System formulation for parallel circuit analysis

dc.contributor.advisorChristoffersen, Carlos
dc.contributor.authorSavalia, Tapankumar Kishorbhai
dc.description.abstractAdvances in communication systems and VLSI circuits increase the performance requirements and complexity of circuits. During the design process, there is a need to perform computationally demanding numerical simulations to verify the functionality of circuits under design. One way to reduce computing time is to use parallel processing. This thesis discusses different techniques for parallel circuit analysis with emphasis in the formulation of equations for a circuit decomposed in subcircuit blocks. For manually decomposed circuit, this thesis introduces two approaches to formulate circuit equations. The two formulations allow to independently analyze each subcircuit block by periodically exchanging information with a master process. A node-tearing process is used to divide the system Jacobian in blocks. The first formulation is base on the nodal voltages and currents at the interface nodes. The second formulation is presented in this thesis for the first time and uses scattering waves to exchange information between subcircuits. The two formulations are described in detail and implemented in a general circuit simulator. Simulation results comparing the performance of the proposed formulations for different circuits are presented. These results indicate that there is no advantage in using waves to exchange information between subcircuits. Moreover, at least with the current software implementation the formulation based on nodal variables is significantly more efficient. This thesis concludes with a road map for future work.en_US
dc.subjectCircuit decompositionen_US
dc.subjectCommunication systemsen_US
dc.subjectNode-tearing formulationen_US
dc.subjectParallel circuit analysisen_US
dc.subjectVLSI circuitsen_US
dc.titleSystem formulation for parallel circuit analysisen_US
dc.typeThesisen_US : Electrical & Computeren_US Universityen_US

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