Show simple item record

dc.contributor.advisorChristoffersen, Carlos
dc.contributor.authorSharma, Anuj
dc.date.accessioned2016-11-01T12:40:20Z
dc.date.available2016-11-01T12:40:20Z
dc.date.issued2016
dc.identifier.urihttp://knowledgecommons.lakeheadu.ca/handle/2453/797
dc.description.abstractA current reference circuit is a basic building block in analog, digital and mixed-signal design systems. This work focuses on one type of integrated CMOS current reference circuit. This source only uses one type of MOSFET transistor and is suitable to produce very low currents in the order of nano Amperes. Despite being used in several works in the literature, there is no clear methodology to produce an optimal design for this source. With the absence of a design methodology, process variability becomes critical in affecting the performance of the current source. This variability issue is prominent in nanometer scaling of the technology. This work addresses that problem by developing a methodology to achieve a design with low area and low sensitivity to transistor mismatch. Presented are the sensitivity and mismatch analysis, methodology, design example and results in addi- tion to performance figures for a lesser sensitive circuit as compared with its traditional counterpart. Future scope of research has also been included in this thesis.en_US
dc.language.isoen_USen_US
dc.subjectCMOS current reference circuiten_US
dc.subjectSimple current sourceen_US
dc.subjectMOSFET transistoren_US
dc.titleA Design Methodology for Low Power CMOS Current Sourceen_US
dc.typeThesis
etd.degree.nameMaster of Scienceen_US
etd.degree.levelMasteren_US
etd.degree.disciplineEngineering : Electrical & Computeren_US
etd.degree.grantorLakehead Universityen_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record