The design of fast-transient cap-less low-dropout voltage regulators

Abstract

This thesis provides a theoretical and experimental study of cap-less LDO regulators

for high speed applications. The three different architectures used in LDO designs are re- viewed in detail along with their advantages and disadvantages. Theoretical analysis of each

architecture is covered along with a review of state of the art designs. The thesis presents two cap-less designs. The first design uses a dual loop architecture to enable fast transient response and high current capability of which the current loop offers fast transient while the voltage loop provides regulation. The second proposed LDO utilizing a hybrid architecture of which the digital part introduces a fast transient approximation algorithm demonstrating significant speed improvements over traditional algorithms. The design is optimized for low clock frequency applications and high output current. Both LDO designs are manufactured using the TSMC 180 nm technology and demonstrate both simulation and measurement results.